In the context of the invention, a carrier layer is regarded as a layer on which the semiconductor layer sequence is arranged in the course of its processing. In particular, this is done prior to a singulation into semiconductor chips which comprise semiconductor chip regions and the latter in turn comprise a part of the semiconductor layer sequence. In particular, the semiconductor layer sequence is intended for forming a plurality of semiconductor chip regions. Said semiconductor chips may subsequently be processed further for semiconductor components. The carrier layer is at any rate to be differentiated from a growth substrate of the abovementioned semiconductor layer sequence.
A carrier layer of this type should be well matched to the semiconductor layer sequence with regard to its coefficient of expansion, in order to avoid strains that are damaging to the semiconductor layer sequence in the event of heating, and have a high thermal conductivity, in order to ensure a good dissipation of heat from the semiconductor layer sequence, in particular the later semiconductor chip (i.e., the chip formed after singulation). For the case where the electrical contact connection of the semiconductor layer sequence is effected through the carrier layer, the electrical conductivity thereof is to be chosen to be appropriately high.
Carrier layers made of semiconductor materials, such as Ge or GaAs, and made of metals, such as Mo or CuW, are known, by way of example.
If metallic carrier layers are used, which usually have a high thermal conductivity, then during singulation, which is often effected by sawing, the risk may be increased of metal slivers or warpage arising on the metal, which render the semiconductor chip unusable, for example due to a short circuit. Frequently, the coefficient of thermal expansion is also inadequately matched to the semiconductor layer sequence and strains may arise between the carrier layer and the semiconductor layer sequence in the event of heating, which have a damaging effect on the semiconductor layer sequence.
By contrast, semiconductor materials, in comparison with metals, often have lower thermal or electrical conductivities and often have a lower mechanical stability, in particular with regard to brittlements, thereby increasing the risk of damage to the semiconductor layer sequence and thus the later semiconductor chips. With regard to the coefficients of thermal expansion, however, semiconductor materials are usually better matched to the semiconductor layer sequence than metals.
Furthermore, a chip carrier made of an electrically insulating AlN ceramic is known, on which semiconductor chips can be arranged after singulation. These chip carriers may have a conductor structure that enables the semiconductor chip to be electrically contact-connected from that side of the chip carrier which is opposite to the chip. Said conductor structure may comprise plated-through holes through the chip carrier, so-called vias, which are filled with tungsten. Chip carriers of this type are distinguished by a good thermal conductivity. With regard to their coefficients of expansion, chip carriers of this type can be matched to the semiconductor layer sequence by means of suitable process implementation during production. Since each individual chip is assigned a chip carrier of this type, the production of such chips is cost- and time-intensive.